Methods and apparatus for generating test instruction sequences

Details Methods and apparatus for generating test instruction sequences Methods and apparatus for generating test instruction sequences

2007-10-30

2007-10-30

Bonzo, Bryce P (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C703S026000

Reexamination Certificate

active

10727781

ABSTRACT:
Methods and apparatus are provided for automatically generating instruction sequences for verifying the operation of a processor, such as a central processing unit, a processor core, a graphics accelerator, or a digital signal processor. The instruction sequences can also be used to verify the operation of tools associated with implementing a processor. Test parameters are used to combine test fragments to generate test instructions. Check instructions are also provided to immediately identify faults encountered during operation.

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