Electronic digital logic circuitry – Reliability – Fail-safe
Reexamination Certificate
2000-04-04
2003-03-04
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Reliability
Fail-safe
C326S021000, C326S056000, C710S052000
Reexamination Certificate
active
06529032
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to parallel processing of I/O ports in an electronic system and more specifically to the problems associated with electronic isolation between circuits when I/O ports of distinct, separate controllers are connected in common in an electronic system.
In known electronic systems, parallel processors or controllers are sometimes used to perform or control the functions of the system and in other applications multiple processors are used where redundancy of the system is desired. A drawback to this functionality or redundancy is that a number of the I/O ports of the separate processors or controllers may be electrically connected together creating common I/O points.
For example, in a system using redundant processors, a first processor can be characterized as a primary processor and a second processor can be characterized as a secondary processor. As long as the primary processor is functioning properly, it is possible to leave the secondary processor in a powered down state. However, the I/O ports of the powered down processor are still electrically connected to the active circuit at the common I/O points and the powered down processor may be re-powered by the active processor through the common I/O points, which is known as backdrive current. Backdrive currents may result in processing errors and increased power consumption by the electronic system. It would be desirable to eliminate the detrimental effects of backdrive currents produced by secondary processors and controllers while retaining the full I/O capabilities and diagnostic features of the redundant system.
BRIEF SUMMARY OF THE INVENTION
An input/output (I/O) port for electrical interconnection with multiple similar ports includes an input read circuit, an output drive circuit, a circuit to control the port for input or output mode by electrically disconnecting the output drive circuit from the port, and a back drive current protection circuit placed in series between an external I/O line and the input read and output drive circuits.
REFERENCES:
patent: 4761565 (1988-08-01), Kannegundla
patent: 5146563 (1992-09-01), Donaldson et al.
patent: 5218682 (1993-06-01), Frantz
patent: 5397941 (1995-03-01), Merrill
patent: 5880602 (1999-03-01), Kaminaga et al.
patent: 6121795 (2000-09-01), Curd et al.
Cieri Joseph J.
Cruickshank Ancil B.
Gareis Ronald E.
Smith Michael G.
Tuten A. Alan
Armstrong Teasdale LLP
Chang Daniel D.
General Electric Company
Vick, Esq. Karl A.
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