Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2002-09-27
2004-07-06
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S230060, C365S196000
Reexamination Certificate
active
06760247
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to apparatus and methods for writing and/or reading row or column data to or from a memory array.
BACKGROUND OF THE INVENTION
In semiconductor memory devices, data is read from or written to memory cells in the device according to decoded address information and various other control signals. Such memory devices are used for storage of data and or program code in personal computer systems, embedded processor-based systems, video image processing circuits, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (1T1C) configurations, in which each memory cell includes one or more access transistors, as is generally known. The ferroelectric memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, wherein the access transistor or transistors, typically MOS devices, are operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding circuitry.
Such ferroelectric memory devices provide non-volatile data storage where data memory cells are constructed using ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an,electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complimentary bitline and a plateline signal voltage. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor charged to a binary “0” and that of the capacitor charged to a binary “1”. The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered and applied to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device.
Connection of the ferroelectric cell capacitor between the plateline and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, the sense amplifier can measure the charge applied to the cell bit lines and produce either a logic “1” or “0” at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the cell following each read operation. To write data to the cell, an electric field is applied to the cell capacitor by a sense amp or write buffer to polarize it to the desired state. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. In such a conventional ferroelectric memory device, row decoder circuitry is connected to a first side of a ferroelectric memory cell of interest and the second side is connected to IO circuitry using a sense amp. During a write operation, the row decoder provides plateline pulse signals to the first side of each ferroelectric cell in a data row and the other sides are connected to the write data. In a read operation, the decoder provides plate line pulses to the first side of each ferroelectric memory cell in a data row, and sense amplifiers are connected to the other side of the cells to read a row of stored data bits in parallel fashion. In a single read operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row.
However, there are situations in which only the data in one or a few columns of the array is needed. For example, in image processing applications it may be desirable to read the first data bit from a number of different rows, such as the first bit from 16 data rows. In conventional memory architectures, a single parallel read of a column of data is not possible. Instead, this would require 16 read operations, one for each of the 16 rows. Thus, the effective read out speed for column data is much slower than for row data in existing memory devices. A parallel situation exists for write operations, wherein conventional memory architectures require 16 write operations just to write a column of 16 cells. Accordingly, there is a need for improved memory devices and methodologies, by which parallel column and row data accesses can be done at comparable speeds for read and/or write operations.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in simplified form as a prelude to the more detailed description that is presented later. The invention relates to memory devices and methods in which rows or columns of data can be accessed for reading and/or writing in a single memory operation, by which the above mentioned and other disadvantages associated with conventional memory devices may be mitigated or overcome.
One aspect of the invention relates to memory devices comprising an array with memory cells arranged in columns and rows, where individual memory cells are coupled with a single row line and a single column line. Row sense amps are provided, individually comprising a row sense amp input coupled with one of the row lines, where the row sense amps are operable to sense a memory cell data state during a column read operation and to provide write data during a column write operation. Column sense amps are also provided, which individually comprise a column sense amp input coupled with one of the column lines, and which are adapted to sense a memory cell data state during a row read operation and to provide write data during a row write operation. A decoder is also provided, which comprises a plurality of row decoder outputs coupled with the row lines and column decoder outputs coupled with the column lines. The decoder operates to provide a plateline signal to one of the row decoder outputs according to address information for a selected row during a row read or write operation, and to provide a plateline signal to one of the column decoder outputs according to add
Brady III W. James
Garner Jacqueline J.
Le Thong Q.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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