Methods and apparatus for fault diagnosis in self-testable syste

Details Methods and apparatus for fault diagnosis in self-testable syste Methods and apparatus for fault diagnosis in self-testable syste

1997-10-09

1998-11-03

Beausoliel, Jr., Robert W.

Excavating

371 2233, G01R 3128

Patent

active

058319921

ABSTRACT:
An analytical fault diagnostic methodology for use in complex VLSI chips. The method assumes a scan design environment and is capable of locating errors to the scan flops that capture the errors during test, independently of the number of errors that the circuit-under-test produces. The methodology is also capable of identifying the test vector or vectors under which the errors are generated. The apparatus which is designed to implement the method is also described. As the apparatus requires little hardware, the method is practical for chip level applications.

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