Methods and apparatus for executing code while avoiding...

Details Methods and apparatus for executing code while avoiding... Methods and apparatus for executing code while avoiding...

2007-02-13

2007-02-13

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S260000, C712S244000, C718S107000, C718S108000

Reexamination Certificate

active

10386593

ABSTRACT:
Mechanisms and techniques operate in a scalable or non-scalable processing architecture computerized device to execute critical code while overcoming interference from interruptions. A critical signal handler is registered and a non-operating system thread sets a value of a critical code register to indicate a critical execution condition. The non-operating system thread then executes a critical code section until an interruption occurs. In response to the interruption to the critical code section, an operating system thread detects if the critical code register is equivalent to a critical execution condition and if so, sets the value of the critical code register to indicate a critical execution failure. Upon returning to execution of the critical code section, the critical code section attempts to execute a contingent instruction in the critical code section that is contingent upon the value of the critical code register. The attempted execution of the contingent instruction triggers a critical trap signal when the critical code register is set to a value that indicates the critical execution failure. The critical execution signal handler processes the critical trap signal to avoid any interference that may have been caused by the interruption.

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Brian N. Bershad, David D. Redell and John R. Ellis, Fast Mutual Exclusion for Uniprocessors, ASPLOS V—Oct. 1992/MA, USA.

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