Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2000-04-28
2003-11-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
Reexamination Certificate
active
06647518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to a bit error rate estimator and methods for its use. More particularly, the present invention relates to a programmable bit error rate estimator having automatic error correction, operating speeds independent of the length of the pattern being transmitted, and flexible inter-path implementation.
2. Background Art and Technical Problems
Communications systems use channels for high speed transmission of data. For example, SONET (Synchronous Optical Network) applications use fiber optic channels for high speed transmission of data. In order to have efficient operation of the channels in such a network, the routing paths must be monitored by measuring the number of errors per unit of time. However, even if the channel itself is efficient, interfaces to the transmitter and/or receiver of a network system may lack efficiency. In this respect, the errors occurring within the entire network system must be accounted for. The number of errors in a communications system may be measured as a bit error rate, which is a ratio of error bits to a number of bits transmitted. In the past, the bit error rate has been measured at the receiver end of a communications system.
For example, one known bit error rate estimator system includes programming equipment on the transmitter side of a network and estimating equipment on the receiver side of the network. This system generates a reference pattern of data at the receiver and compares that reference pattern to the actual pattern of data transmitted from the transmitter. The bit errors introduced within the network are accounted for by a counter. At this point, system administrator must manually read and use the comparison data from the bit error rate estimator equipment. In this way, the prior art system has manual error correction.
In addition, the prior art bit error rate estimator system does not use checkpoints within the network, but rather is limited to making error estimations only at the transmitter and receiver ends. Consequently, the system cannot easily be implemented within the transmitter-receiver path, due to cost, power usage, and physical location of the equipment at the transmitter and receiver ends. By way of illustration, programming equipment of the bit error rate estimator may be located in Los Angeles while the estimating equipment may be located in New York City. Accordingly, there would be no bit error rate checkpoints within the path between Los Angeles and New York City. Thus, the prior art system lacks flexible inter-path implementation.
In addition, the N bit counter used in this prior art system and many other systems limits the overall speed by which the system can operate. The number of bits N, and thus the pattern length of 2
N
, is inversely proportional to the speed at which the system may operate. In this way, the speed of the system is limited by the number of bits N, or the pattern length of 2
N
bits. Furthermore, the known system discussed above is expensive to implement.
Due to the need for efficient high speed communications and in view of the problems associated with the prior art, a need exists for a programmable bit error rate estimator capable of automatic error correction, capable of operating at speeds that are independent of pattern length, and having flexible inter-path and cost-effective implementations.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a programmable bit error rate estimator having automatic error correction and flexible inter-path implementation is provided. The bit error rate estimator of the present invention uses an initialization configuration for a reference pattern generator of a receiver in such a way as to eliminate the need for an N bit counter. One option allows the system administrator to monitor the errors in the system and take steps as deemed necessary. Another option counts the errors in a specified amount of time and generates a new reference pattern if the number of errors reaches a predetermined maximum amount. Additionally, the bit error rate estimator of the present invention may be implemented at many router points of a network. Thus, the bit error rate estimator of the present invention provides automatic error detection, programmability, and flexible inter-path implementation.
REFERENCES:
patent: 4283620 (1981-08-01), Drescher et al.
patent: 5619509 (1997-04-01), Maruyama et al.
patent: 5732089 (1998-03-01), Negi
patent: 5761216 (1998-06-01), Sotome et al.
patent: 5764651 (1998-06-01), Bullock et al.
Conexant Systems Inc.
Hale Kelly H.
Kind Keith
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