Methods and apparatus for error checking code decomposition

Details Methods and apparatus for error checking code decomposition Methods and apparatus for error checking code decomposition

2006-04-12

2009-12-15

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S759000, C714S781000

Reexamination Certificate

active

07634705

ABSTRACT:
Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.

REFERENCES:
patent: 6519738 (2003-02-01), Derby
patent: 2003/0056158 (2003-03-01), Yue
NB9406267:‘Technique for Cyclic Redundancy Check Modification Useful in Certain Data Networks.’IBM Technical Disclosure Bulletin, Jun. 1994, US;vol. No. 37 ,Issue No. 6B.
NN8805458:‘Method to Provide Software Calculation of a 32-Bit Frame Check Sequence, a Byte at a Time,’IBM Technical Disclosure Bulletin, May 1988, US, vol. No. 30, Issue No. 12.
Gurindar Singh Sohi, “High-Bandwidth Interleaved Memories for Vector Processors—A Simulation Study”, IEEE Transactions on Computers, vol. 42, No. 1, Jan. 1993.
Terry Ritter, “The Great CRC Mystery”, Dr. Dobb's Journal of Software Tools, Feb. 11(2); 26-34, 76:83, downloaded Apr. 24, 2007, 1986.

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