Methods and apparatus for error checking code computation

Details Methods and apparatus for error checking code computation Methods and apparatus for error checking code computation

2006-09-25

2010-11-23

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000, C714S776000, C714S807000

Reexamination Certificate

active

07840880

ABSTRACT:
Methods and apparatus are provided for more efficiently computing error checking codes such as cyclic redundancy checks (CRCs). Based on particular characteristics of CRCs, an input sequence is intelligently divided into a series of subsequences. Each subsequence gets selected bits from the input sequence. The error checking code is calculated on each subsequence. The results are bit-interleaved and an error checking code is calculated over this interleaved result to obtain the error checking code over the entire sequence.

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Shieh et al., “A Systematic Approach for Parallell CRC Computations”, Journal of Information Science and Engineerings, 17, 445-461 (2001).

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