Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-06-30
2008-09-16
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S125000, C711S133000, C711S137000
Reexamination Certificate
active
07426612
ABSTRACT:
Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory region prior to generating new code associated with the initialized memory region. Coherence code associated with the initialized memory region is generated. The new code associated with the initialized memory is generated. At least one of the new code and the coherence code is executed. Other embodiments may be described and claimed.
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Hanley Flight & Zimmerman, LLC.
Intel Corporation
Kim Matt
Krofcheck Michael C
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