Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-11-01
2005-11-01
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S757000
Reexamination Certificate
active
06961888
ABSTRACT:
Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.
REFERENCES:
patent: 3542756 (1970-11-01), Gallager
patent: 3665396 (1972-05-01), Forney, Jr.
patent: 4295218 (1981-10-01), Tanner
patent: 5157671 (1992-10-01), Karplus
patent: 5271042 (1993-12-01), Borth et al.
patent: 5293489 (1994-03-01), Furui et al.
patent: 5313609 (1994-05-01), Baylor et al.
patent: 5396518 (1995-03-01), How
patent: 5457704 (1995-10-01), Hoeher et al.
patent: 5526501 (1996-06-01), Shams
patent: 5615298 (1997-03-01), Chen
patent: 5671221 (1997-09-01), Yang
patent: 5860085 (1999-01-01), Stormon et al.
patent: 5864703 (1999-01-01), van Hook et al.
patent: 5867538 (1999-02-01), Liu
patent: 5892962 (1999-04-01), Cloutier
patent: 5933650 (1999-08-01), van Hook et al.
patent: 5968198 (1999-10-01), Hassan et al.
patent: 6002881 (1999-12-01), York et al.
patent: 6073250 (2000-06-01), Luby et al.
patent: 6195777 (2001-02-01), Luby et al.
patent: 6247158 (2001-06-01), Smallcomb
patent: 6266758 (2001-07-01), van Hook et al.
patent: 6298438 (2001-10-01), Thayer et al.
patent: 6339834 (2002-01-01), Crozier et al.
patent: 6397240 (2002-05-01), Fernando et al.
patent: 6438180 (2002-08-01), Kavcic et al.
patent: 6473010 (2002-10-01), Vityaev et al.
patent: 6484284 (2002-11-01), Smallcomb
patent: 6526538 (2003-02-01), Hewitt
patent: 6633856 (2003-10-01), Richardson et al.
patent: 6718504 (2004-04-01), Coombs et al.
patent: 6731700 (2004-05-01), Yakhnich et al.
patent: 6754804 (2004-06-01), Hudepohl et al.
patent: 2004/0034828 (2004-02-01), Hocevar
Richardson et al. The capacity of low-density parity-check codes under message-passing Decoding, IEEE Transactions of Information Theory; pp.: 599-618, Feb. 2001, (same inventor) whole document.
Paranchych et al., Performance of a digital symbol synchronizer in cochannel interference and noise, IEEE Transactions on Communications, pp.: 1945-1954; Nov. 2000, whole document.
NN77112415. Digital Encoding of Wide Range Dynamic Analog Signals, IBM Tech. Disclosure Bulletin, Nov. 1, 1997, vol. No. 20; Issue No. 6; pp. 2415-2417, whole document.
NN9210335. Hierarchical Coded Modulation of Data with Fast Decaying Probability Distributions, IBM Tech. Disclosure Bulletin, Oct. 1992, vol. No. 35; Issue No. 5; pp. 335-336, whole document.
Sorokine, V. et al. Innovative coding scheme for spread-spectrum communications, The Ninth IEEE International Symposium on Indoor and Mobile Radio Communications, pp.: 1491-1495, vol. 3; Sep. 1998, whole document.
T. Moors and M. Veeraraghavan, “Preliminary specification and explanation of Zing: An end-to-end protocol for transporting bulk data over optical circuits”, pp. 1-55 (May 2001).
T. Richardson and R. Urbanke, “The Capacity of Low-Density Parity-Check Codes under Message-Passing Decoding”, pp. 1-44 (Mar. 2001).
T. Richardson, A. Shokrollahi, R. Urbanke, “Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes”, pp. 1-43 (Mar. 2001).
T. Richardson and R. Urbanke, “An Introduction to the Analysis of Iterative Coding Systems”, pp. 1-36.
Saied Hemati, Amir H. Banihashemi, VLSI circuits: Iterative decoding in analog CMOS, Proceedings of the 13thACM Great Lakes Symposium on VLSI Apr. 2003, pp.: 15-20.
Mohammed M. Mansour, Naresh R. Shanbhag, Session 11: Low-power VLSI decoder architectures for LDPC codes, Proceedings of the 2002 international symposium on Low power electronics and design Aug. 2002, pp.: 284-289.
W. W. Peterson and E.J. Weldon, Jr., “Error-Correcting Codes”, Second Edition, The Massachusetts Institute of Technology, pp212-213,261-263, 263, 263, (1986).
R. Blahut, “Theory and Practice of Error Control Codes”, Library of Congress Cataloging in Publication Data, pp-47-49, (May 1984).
Jin Hui
Novichkov Vladimir
Richardson Tom
Baker Stephen M.
Flarion Technologies, Inc.
Straub Michael P.
Struab & Pokotylo
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