Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1992-11-13
1995-12-05
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326 86, 326 90, 375257, 333 32, H03K 1716, H03K 190175
Patent
active
054732646
ABSTRACT:
A circuit arrangement and methods for sensing whether line terminator devices are present at terminal ends of high speed communications pathways, and enabling a switching terminator in accordance therewith, are disclosed. In one embodiment, the communications pathway comprises a Small Computer System Interface (SCSI) bus comprising internal and external bus segments and bus control lines, including a reset line consisting of internal and external reset line segments. First and second system reset signals are supplied from a central processor unit (CPU) to various system components. Line terminator devices may or may not be coupled to the ends of the internal and external bus segments. The first system reset signal is directed to first and second transistors coupled together in an "upside down" collector-to-emitter configuration comprising a two-quadrant bidirectional switch which opens upon assertion of the first system reset signal. The internal and external reset request lines are coLtpied to the collectors of the first and second transistors respectively, and further form inputs to a NAND gate. First and second resistors having impedances large relative to the impedance of line terminator devices are coupled as pull-down resistors between both internal and external reset request lines forming the inputs to the NAND gate and ground. The NAND gate together with the first and second resistors produce a DECISION output signal for the 4 different possible input combinations of SCSI bus terminations, DECISION being either "connect terminator" or "don't connect terminator". The DECISION output signal is latched or otherwise stored upon deassertion of the second system reset signal, and is subsequently routed to an enable pore of the switching terminator to engage the terminator element therein. The two-quadrant switch is closed upon deassertion of the second system reset signal, recoupling the internal and external reset lines.
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Adams Dale
Banks Jano
Mader Thomas B.
Apple Computer Inc.
Larwood David J.
Roseen Richard
Westin Edward P.
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