Methods and apparatus for early loop bottom detection in...

Details Methods and apparatus for early loop bottom detection in... Methods and apparatus for early loop bottom detection in...

2008-07-29

2008-07-29

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

10786968

ABSTRACT:
Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offset and configured to decode instructions following the loop setup instruction, each having an instruction address, to obtain an instruction width, registers for holding the loop setup instruction address and the loop bottom offset, and a loop bottom detector, responsive to a current instruction address, a current instruction width, the loop setup instruction address and the loop bottom offset, configured to determine if a next instruction is a loop bottom instruction.

REFERENCES:
patent: 6671799 (2003-12-01), Parthasarathy
patent: 6748523 (2004-06-01), Singh et al.
patent: 2002/0078333 (2002-06-01), Inoue et al.
patent: 2005/0102659 (2005-05-01), Singh et al.
Derived Logic Functions and Gates, May 28, 2003.

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