Methods and apparatus for dynamic instruction controlled...

Details Methods and apparatus for dynamic instruction controlled... Methods and apparatus for dynamic instruction controlled...

2011-05-10

2011-05-10

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: processing

Processing control

C712S203000, C712S215000, C712S029000

Reexamination Certificate

active

07941648

ABSTRACT:
A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

REFERENCES:
patent: 6216220 (2001-04-01), Hwang
patent: 6658551 (2003-12-01), Berenbaum et al.
patent: 2001/0042187 (2001-11-01), Tremblay

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