Methods and apparatus for debugging a system with a hung...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Reexamination Certificate

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07412624

ABSTRACT:
Methods and apparatus are provided to facilitate debugging of a system with a hung data bus. A register scan chain is used to read data from logic blocks of the hung system. The scan chain is also used to write data into the logic blocks, possibly resetting a subset of those blocks or otherwise causing them to exit the hung state. The resetting may terminate the hung instruction in a manner that allows subsequent instructions to be executed, including entry into debug mode.

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patent: 6530047 (2003-03-01), Edwards et al.
patent: 6539497 (2003-03-01), Swoboda et al.
patent: 6715105 (2004-03-01), Rearick
patent: 6988232 (2006-01-01), Ricchetti et al.
patent: 7069485 (2006-06-01), Whetsel et al.
patent: 2003/0159096 (2003-08-01), Balzer
patent: 2003/0163773 (2003-08-01), O'Brien et al.

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