Boots – shoes – and leggings
Patent
1992-10-19
1994-05-17
Gossage, Glenn
Boots, shoes, and leggings
395425, 395550, 364DIG1, G06F 1342, G06F 1300
Patent
active
053135946
ABSTRACT:
A computer system is optimized to perform fast block transfers between modules including local memories that communicate over a multi-master global synchronous bus. Write operations are speeded up by a destination module sending a "ready-to-accept-data" signal before each write request. During a given clock period during which a source module delivers a data word to the bus, the destination module asserts this "ready" signal to indicate to the source module that the destination module is ready for the source module to deliver another word during another, subsequent clock period. The source module can deliver one word per clock period, and the destination module can receive one word per clock period. During a block write, only a starting address for a first word transferred is transmitted, with a counter at both source and destination modules counting each word transferred. Part of the address bus is not used for addresses and instead is used for data. Local memory is accessed in each module at the rate of one access per clock period. The bust performs one transfer per clock cycle, with successive transfers pipelined on the bus to minimize dead cycles.
REFERENCES:
patent: 3820079 (1974-06-01), Bergh et al.
patent: 4099236 (1978-07-01), Goodman
patent: 4418386 (1983-11-01), Vrielink
patent: 4481580 (1984-11-01), Martin et al.
patent: 4485438 (1984-11-01), Myrmo et al.
patent: 4591977 (1986-05-01), Nissen et al.
patent: 4722051 (1988-01-01), Chattopadhya
patent: 4777595 (1988-10-01), Strecker et al.
patent: 4807109 (1989-02-01), Farrell et al.
patent: 4864496 (1989-09-01), Triolo et al.
patent: 4924427 (1990-05-01), Savage et al.
patent: 4928224 (1990-05-01), Zulian
patent: 4939692 (1990-07-01), Kendall
patent: 5019966 (1991-05-01), Saito et al.
Case et al, "Choosing Memory Architectures to Balance Cost and Performance", Microrprocessor Reports, vol. 2, No. 9, Sep. 1988, pp. 6-9.
.mu.PD70320/322 (V25.TM.) 16 Bit, Single-Chip CMOS Microcomputers, NEC Electronics Inc., Sep. 1987, pp. 1-76.
Alantec, Inc.
Gossage Glenn
LandOfFree
Methods and apparatus for data transfer between source and desti does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for data transfer between source and desti, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for data transfer between source and desti will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-884392