Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2002-03-20
2004-12-14
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
06832300
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to processing systems and, more particularly, to cache control in a processor configured to access a cache asynchronously.
BACKGROUND OF THE INVENTION
Cache memory on a large multi-processor die can be allocated for a plurality of purposes, depending on roles assigned to the various on-chip processors. For example, one of the processors might be used as a special-purpose processor performing encryption and decryption while another is performing computations using a large database. In such case, the encryption processor would need very little cache memory to perform its function, while the computation-intensive processor would use as much cache as could be made available. Thus it frequently is desirable to allocate differing amounts of cache memory to different processors on the same chip.
Varying cache size, however, also can result in varying latency, that is, time needed to return data from cache memory in response to a processor request for the data. When cache memory allocated to a particular processor is increased, more time may be needed to locate and return to the processor a data line residing in a relatively remote cache location. Thus cache latencies typically are generated in varying lengths in response to requests by a processor, dependent on the location of a requested data line in the cache. When a cache memory is accessed, latencies of varying lengths also can arise if the cache voltage is different from the processor core voltage. Such a situation can occur when variable voltage is used as a power control mechanism.
A traditionally designed processor, however, accesses cache via a pipeline that is assumed by the processor to generate a fixed latency. Such processors are configured to wait during cache access requests, for a fixed time period corresponding to the assumed pipeline latency. Even if varying a cache size and/or cache voltage differential might result in significant numbers of shortened latencies, a conventional processor nevertheless would need to assume the pipeline latency to be a fixed maximum value in order to accommodate a range of possible cache latencies.
Such a processor frequently could be required to wait for cache data longer than actually necessary, thus slowing processor performance. Where an on-die cache is allocated in varying amounts to a plurality of on-die processors, accommodation of unnecessarily long processor waits for cache data also can result in cache under-utilization. It would be desirable, then, to allow a processor to adapt to cache latencies of varying lengths and to take advantage of relatively short latencies. Such capability would be particularly desirable in an single-die multiprocessing system in which on-die cache, a precious resource, is allocated according to respective needs of the processors.
SUMMARY OF THE INVENTION
In one preferred form, a processing system includes a cache controller for managing requests for data from a cache memory by a processor. The cache controller includes an access queue configured to hold requests for data pending asynchronous retrieval of the requested data from the cache memory. The cache controller also includes an exit queue configured to hold the requested data retrieved from the cache memory until released to the processor.
The above-described queuing arrangement allows data lines to be retrieved from cache memory without a pipeline, while latencies are minimized. More than one cache memory request can be outstanding at one time, and data requested from the cache memory can be returned to the processor in any order. Thus multiprocessor performance need not be slowed down by unnecessarily long waits for latencies. The above queuing scheme is simple yet tailored to facilitate asynchronous cache access in a multiprocessing environment.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
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