Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-01-09
2007-01-09
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S119000, C711S003000, C709S218000, C709S219000
Reexamination Certificate
active
10321078
ABSTRACT:
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for transmitting memory cancels to memory controllers in the various clusters of a multiple cluster system are provided. In one example, memory cancels are transmitted between clusters when it is determined that a memory line associated with a probe is dirty. The memory cancel directs the memory controller to no longer proceed with a data fetch from main memory. In another example, memory cancels are transmitted at a home cluster based on information in a coherence directory in order to more quickly end a data fetch.
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Glasco David B.
Kota Rajesh
Beyer Weaver & Thomas LLP.
Chery Mardochee
Newisys Inc.
Padmanabhan Mano
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