Methods and apparatus for bus mastering and arbitration

Details Methods and apparatus for bus mastering and arbitration Methods and apparatus for bus mastering and arbitration

2005-02-15

2005-02-15

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C700S003000

Reexamination Certificate

active

06857035

ABSTRACT:
Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

REFERENCES:
patent: 6393506 (2002-05-01), Kenny
patent: 6681283 (2004-01-01), Thekkath et al.
patent: 6701398 (2004-03-01), Wyland
patent: 6772254 (2004-08-01), Hofmann et al.
“A multistage hierarchical distributed arbitration technique for priority-based real-time communication systems” by Cena, G.; Valenzano, A. (abstract only) Publication Date: Dec. 2002.*
“Architecture and bus-arbitration schemes for MPEG-2 video decoder” by Jui-Hua Li; Nam Ling (abstract only) Publication Date: Aug. 1999.*
ARM, “Multi-Layer AHB: Overview,” ARM DVI 0045A, ARM Limited, © 2001, pps. 1-12.
ARM, “AMBA Specification (rev. 2.0),” ARM IHI 0011A, ARM Limited, © 1999, pps. ii-5-38.

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