Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2011-01-04
2011-01-04
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S220000, C711S206000, C711S125000, C711SE12058, C711SE12002
Reexamination Certificate
active
07865692
ABSTRACT:
A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.
REFERENCES:
patent: 2002/0013691 (2002-01-01), Warnes
Conte Thomas M.
Larin Sergei Yurievich
Pechanek Gerald George
Altera Corp.
Bragdon Reginald G
Faal Baboucarr
Priest & Goldstein PLLC
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