Methods and apparatus for allowing simultaneous memory...

Details Methods and apparatus for allowing simultaneous memory... Methods and apparatus for allowing simultaneous memory...

2006-04-18

2009-12-22

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S157000, C711S219000

Reexamination Certificate

active

07636817

ABSTRACT:
Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure. Memory is divided into blocks having sequential addresses based on the number of simultaneous memory access specified, e.g. base addresses at A, A+B, A+2B, A+3B. Individual slave side arbiters are assigned to each block of memory. Addresses for memory accesses associated with master components or master ports are modified to allow simultaneous access to multiple memory locations.

REFERENCES:
patent: 7426709 (2008-09-01), Ganesan
Gurindar Singh Sohi, “High-Bandwidth Interleaved Memories for Vector Processors—A Simulation Study”, IEEE Transactions on Computers, vol. 42, No. 1, Jan. 1993.

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