Methods and apparatus for a system clock divider

Details Methods and apparatus for a system clock divider Methods and apparatus for a system clock divider

2007-01-30

2007-01-30

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S322000, C713S601000

Reexamination Certificate

active

10681675

ABSTRACT:
A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.

REFERENCES:
patent: 3867614 (1975-02-01), White
patent: 4947411 (1990-08-01), Shiraishi et al.
patent: 5410683 (1995-04-01), Al-Khairi
patent: 6060902 (2000-05-01), Albu et al.
patent: 6111595 (2000-08-01), Hertrich
patent: 6337600 (2002-01-01), Shigemori et al.
Dallas Semiconductor, DS1075 EconOscillator/Divider, Nov. 16, 1997, pp. 1-18.

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