Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Patent
1996-06-17
2000-09-19
Peikari, B. James
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
711173, 711171, 711172, G06F 1202
Patent
active
06122717&
ABSTRACT:
A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading. An arbiter receives the cell available signals, and it generates control signals to select one of the FIFO memory cores. An output selection circuit utilizes the control signals to output data from one of the FIFO memory cores. The FIFO memory device further includes a plurality of output pins that receive the cell available signals and that receive the cell size information.
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QS6810 Advance Information Datasheet, Rev. 1.1, Apr., 1995, entitled: "4:1 ATM Multiplexer/Demultiplexer (AMDM)".
Au Mario F.
Chan Raymond K.
Integrated Device Technology Inc.
Peikari B. James
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