Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-02
2010-06-29
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S025000, C714S777000
Reexamination Certificate
active
07747926
ABSTRACT:
A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
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Andre Thomas W.
Durlam Mark A.
Salter Eric J.
Wise Loren J.
Everspin Technologies, Inc.
Ingrassia Fisher & Lorenz P.C.
Lamarre Guy J
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