Electrical computers and digital processing systems: memory – Address formation – Varying address bit-length or size
Reexamination Certificate
2006-12-12
2006-12-12
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Varying address bit-length or size
Reexamination Certificate
active
07149873
ABSTRACT:
In one embodiment of the invention, a method is provided to allow an operating system to support both address space layouts of a SAS OS and a MAS OS at the same time, with the choice of which layout type to be used to be made by the application developer. In one embodiment the method includes: selecting one of a mostly private address space (MPAS) model and a mostly global address space (MGAS) model, where if the MPAS model is selected, then a process is permitted to map a shared object in a mostly private address space (MPAS) layout so that the process perceives a behavior as if the process is running on a multiple address space operating system, and where if the MGAS model is selected, then the process is permitted to map a shared object in a mostly global address space (MGAS) layout so that the process perceives a behavior as if the process is running on a single address space operating system.
REFERENCES:
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patent: 6052763 (2000-04-01), Maruyama
patent: 6154818 (2000-11-01), Christie
patent: 6854114 (2005-02-01), Sexton et al.
patent: 2003/0101322 (2003-05-01), Gardner
Ahluwalia Manish
Mohideen Saleem
Bragdon Reginald
Ko Daniel
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