Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-06-23
2009-08-04
Baker, Stephen M (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S781000
Reexamination Certificate
active
07571372
ABSTRACT:
Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically. Since the complexity of parity-based error correction schemes increases disproportionately to the number of potential error events, the present invention meets a long-felt need for a scheme to manage error detection and/or correction in systems (such as magnetic recording applications) where there may be a relatively large number of likely error events, thereby advantageously improving reliability and/or performance in channel communications.
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Zining Wu and Gregory Burd; Error Correction Using Error Detection Codes; U.S. Appl. No. 10/752,339, filed Jan. 6, 2004.
Burd Gregory
Wu Zining
Baker Stephen M
Marvell International Ltd.
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