Methodology to guard ESD protection circuits against...

Details Methodology to guard ESD protection circuits against... Methodology to guard ESD protection circuits against...

2011-01-04

2011-01-04

Fureman, Jared J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000

Reexamination Certificate

active

07864494

ABSTRACT:
An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).

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