Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-06
2003-10-14
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C707S793000, C707S793000
Reexamination Certificate
active
06634008
ABSTRACT:
BACKGROUND OF THE INVENTION
This application relates generally to integrated circuit design systems and methods, and more particularly to an environment for designing integrated circuits.
Integrated circuits have become increasingly complex, and perform ever increasing functions. Indeed, integrated circuits on a single chip now often perform functions which were previously performed by sets of chips or even by one or multiple circuit boards. As single chip integrated circuits now perform functions previously performed by entire systems, these single chips integrated circuits are sometimes referred to as system-on-chip (SOC).
Complex integrated circuits, particularly SOCs, are often designed in terms of blocks, with a number of blocks making up the integrated circuit. The large number of blocks on a single chip, and the complexity of each of the blocks, increases the difficulty of the design and test of the integrated circuit as a whole.
FIG. 1
, for example, is an illustration of an integrated circuit
100
. As shown, the integrated circuit (IC) consists of multiple interconnected blocks
101
,
103
,
105
,
107
,
109
,
111
. Each block typically contains complex circuitry performing complex functions. As illustrated, the integrated circuit of
FIG. 1
contains six blocks. In actuality, an integrated circuit will generally contain many more blocks than illustrated, and will include PAD and PORT cells for the reception and transmission of signals from and to the integrated circuit. The use of six blocks in the integrated circuit
100
of
FIG. 1
is meant to illustrate that an integrated circuit
100
may contain a plurality of blocks. Block
1
101
of the integrated circuit of
FIG. 1
is a block designed and tested specifically for the integrated circuit. Block
2
103
is a block provided by a third party supplier. Block
3
105
is a proprietary block reused from another design from the same manufacturer, and block
4
107
is a block designed and tested by a remote design team. Thus, the integrated circuit of
FIG. 1
includes blocks developed specifically for the integrated circuit
101
, blocks derived from third party sources, blocks previously developed in-house
105
, and blocks designed by remote design teams
107
.
For the integrated circuit to function properly each of the blocks must work with the other blocks in an integrated fashion. In addition, it is desirable that operation of the integrated circuit
100
as a whole be verified prior to actual construction of the physical circuit. Accordingly, each of the blocks must be supported by a testing tool used to verify the functionality of the integrated circuit as a whole. In other words, the methodologies used in the design and tests of each of the blocks independently should preferably have been done using the same methodologies, and at a minimum must have been accomplished using non-contradictory methodologies.
Use of contradictory methodologies is likely to result in substantial rework further along in the design process. For example, a chip may be designed using a specific file format for mask layers. A remote design team, however, may provide a block using a different file format for the mask layer, resulting in an unuseable block.
In order to design and test such an integrated circuit in a timely manner, multiple design teams in geographically distant locations may be used to implement and test the design. In addition, it is desirable to reuse existing blocks, sometimes referred to as block intellectual property (IP), in order to decrease design time and to reduce design associated costs. When implementing a design containing 10,000,000 to 25,000,000 gates, reuse and modification IP blocks become increasingly attractive. Once a block has been developed at great expense and effort it is desirable to reuse that block at a later time.
The use of geographically distant design teams and the reuse of block IP presents several problems. A number of design tools, or methodologies, are available to assist designers in the design process, and the complexity of the designs often mandates the use of such tools. The use of different tools by different design teams during the design process may result in an unusable design. Similarly, the design and test of previously designed blocks may also have utilized different tools, also resulting in an unusable design. Further, design and test tools often require that certain environmental parameters be assigned. Use of the same tools, but with differing environmental parameters, may also result in unworkable or unusable designs.
The determination of the tools and environmental parameters to use in designing an integrated circuit require a great deal of skill and knowledge, often gained by experience. Thus, the use of the tools is sometimes hampered if an individual designer does not have sufficient experience with the various tool sets or their use. Accordingly, design teams often heavily rely on a few specific highly skilled individuals to determine the design flow. The loss of such highly skilled personnel during the design process may inordinately impair the effectiveness of the design team and result in delays in producing the integrated circuit. Work on further integrated circuits may also be delayed due to the lack of a sufficient number of highly skilled personnel.
The use of geographically distant design teams and the use of IP blocks, which may have been developed by third party developers, also presents management problems. The use of distant design teams may result in difficulties in accurately assessing the progress of the various design teams and their allotted tasks. Monitoring the design teams to ensure that the appropriate tools and environmental parameters are being used is also difficult.
SUMMARY OF THE INVENTION
The present invention therefore provides an environment for designing integrated circuits. In one embodiment the present invention comprises an integrated design environment for the design and test of integrated circuits, the integrated circuits being comprised of blocks. The integrated design environment includes a plurality of computers, with the computers including a browser for the display of pages including forms. The integrated design environment also includes at least one methodology server in communication with the plurality of computers. The methodology server includes a page generator generating the pages including forms and additionally including programs responsive to submission of information from the computers using the pages including forms. In one embodiment the programs responsive to submission of information comprise common gateway interface (CGI) programs or scripts. The integrated design environment also includes at least one compute server in communication with the methodology server. The compute serve includes an electronic automation tool, and the compute server executes the electronic design automation tool in response to a request generated by a program resident on the methodology server.
In one embodiment the pages including forms include methodology capture pages. Methodology pages are used to capture executable methodologies. In another embodiment the methodologies have steps the steps including submethodologies, ad the methodologies are attached to blocks of which the integrated circuit is comprised.
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Christie Parker & Hale LLP
Fujitsu Limited
Smith Matthew
Thompson A. M.
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