Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-01
2005-03-01
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06862723
ABSTRACT:
A new method to route a metal line in the layout of an integrated circuit device is achieved. The method comprises providing a layout for an integrated circuit device comprising an array of placed standard cells. Contact/via layer polygons are placed for coupling the standard cells. A line is routed in a metal layer. An antenna effect value is calculated for the line using parameters previously determined from the layout of each the standard cell. The parameters comprise gate area, diode area, metal area, and contact/via area coupled to the line. The gate area, the diode area, the metal area, and the contact/via area are segregated by metal level. The steps of routing and calculating are repeated if the antenna effect value exceeds a specified value. A method to extract parameters is disclosed.
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Cheng Chia Ling
Hou Cliff
Lu Lee Chung
Wang Chung-Hsing
Wang Daisy
Garbowski Leigh M.
Taiwan Semiconductor Manufacturing Company
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