Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-12-20
2005-12-20
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S023000, C703S027000
Reexamination Certificate
active
06978425
ABSTRACT:
A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.
REFERENCES:
patent: 6086628 (2000-07-01), Dave et al.
patent: 6097886 (2000-08-01), Dave et al.
patent: 6110220 (2000-08-01), Dave et al.
patent: 6112023 (2000-08-01), Dave et al.
patent: 6178542 (2001-01-01), Dave
patent: 6289488 (2001-09-01), Dave et al.
Lahiri et al., Fast performance of bus-based system-on-chip communication architectures, Nov. 1999, Computer-aided design 1999, Digest of Technical Papers, IEEE/ACM International Conference, pp.: 566-572.
Xia et al., “Verification of a combinational loop based arbitration scheme in a system-on-chip integration architecture”, Hanuary 2000, VLSI design, 2000, Thirteenth international cinference, pp.: 449-454.
Lahiri et al., “Performance analysis of systems with multi-channel communication architectures”, Jan. 2000, VLSI design, Thirteeth International Conference, pp.: 530-537.
Fornaciari et al., “Power estimation for architectural exploration of HW/SW communicatiuon on system-level busses”, May 1999, Hardware/siftware codesign, (CODES'99) Proceedings of the seventh international workshop, pp.: 152-156.
Lagnese et al., “Architectural partitioning for system level synthesis of integrated circuits”, Jul. 1991, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on□□vol. 10, Issue 7, Page(s):847-860.
Yen et al., “Sensitivity-driven co-synthesis of distributed embedded systems”, Sep. 13-15, 1995, System Synthesis, 1995., Proceedings of the Eighth International Symposium on, Page(s):4-9.
Dey Sujit
Lahiri Kanishka
Lakshminarayana Ganesh
Raghunathan Anand
NEC Corporation
Rossoshek Helen
Sughrue & Mion, PLLC
The Regents of the University of California
Thompson A. M.
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