Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-20
2004-10-26
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06810506
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention relate to the simulation of integrated circuits. More particularly, embodiments of the present invention provide a methodology for stitching reduced-order models of interconnects together.
BACKGROUND ART
Modern large semiconductor devices typically make use of a “bottom up” design philosophy. With such a design approach, individual functional blocks, or “IP blocks” (Intellectual Property blocks) may be designed first, or sometimes independently of the overall chip design. Frequently, such blocks are designed for reuse in many chip designs and may even be bought and sold among chip design companies. Typically, certain IP blocks are designed for fundamental and commonly used purposes.
By combining and interconnecting several IP blocks, along with typically some new design effort, very large integrated circuits, comprising hundreds of thousands of gates, may be rapidly designed. The combination of many blocks, sometimes known as “hierarchies,” is also called a hierarchical design.
When designing integrated circuits, designers typically analyze the design at several stages prior to production. It can cost tens of thousands of dollars to produce a single batch of integrated circuits. Further, the production tools that control the manufacture of a specific integrated circuit, e.g., a set of masks that define the physical outline of the semiconductor regions, can cost a quarter of a million dollars. There is great incentive to analyze and understand the behavior of the integrated circuit prior to expending such sums.
Within each IP block, there will typically be wires interconnecting elements of the IP block. Further, there will generally be wires interconnecting the various IP blocks to one another and to additional circuitry. Importantly, there may also be parasitic behaviors associated with such wires. Such parasitic effects are generally undesirable behaviors due to characteristics of the semiconductor elements or the semiconductor manufacturing process. For example, a wire does not have exactly zero resistance. There is typically some resistance, and perhaps non-negligible inductance and capacitance (reactance) in the wire. Such parasitic effects are typically modeled by small lumped resistors and/or capacitors distributed throughout the circuit in a manner similar to transmission line analysis techniques.
In order to analyze the timing of the integrated circuit design, all such parasitic effects should be considered. For example, a wiring interconnect or “net” running between two IP blocks will typically have a portion in a first IP block, a portion in a second IP block and a portion in between the two blocks. Such a net may have many nodes; each node representing a unique point in the circuit, and each such node being modeled as a combination of resistors, capacitors and/or inductors. All such portions will typically have parasitic effects, and the contributions of all parasitic effects from all portions should be considered in the timing analysis.
Unfortunately, as the number of gates, and hence the number of parasitic devices in the model grow, complete simulation and timing analysis becomes unwieldy. Consequently, timing analysis with a full set of parasitic elements in the model is usually not performed. Likewise, for similar computational reasons, synthesis (a computer implemented software process for translating a design specified in a high level language into fundamental design elements) with delay simulations is generally only performed with highly approximate wire models based on statistics, not the detailed wire models for the actual network parasitics.
Approximations to the parasitics for each hierarchical network segment can be made, but such approximations must be compatible with hierarchical composition. For example, consider approximating each network segment by its Elmore delay (first moment). When these delays are added to effect the hierarchical composition, the result can be grossly incorrect. For example, two simple RC networks with respective Elmore delays R
1
*C
1
and R
2
*C
2
, wiring them in series would yield an Elmore delay of R
1
*C
1
+(R
2
+R
2
)*C
2
, and not the sum of the individual Elmore delays R
1
*C
1
+R
2
*C
2
.
In the prior art, this problem has been somewhat mitigated by using a Reduced Order Model, ROM, at each stage of a design. Typically, a ROM may be generated for each IP block, and used as a model for the parasitic effects of that IP block. This may greatly reduce the number of devices actually modeled, and may allow for accurate timing analysis, and even simultaneous synthesis and delay simulation.
A reduced order model is typically generated by an analysis tool, such as PrimeTime, commercially available from SYNOPSYS of Mountain View, Calif. A drawback to the efficacy of such reduced order models is that a single change to the IP block generally necessitates the entire ROM to be recomputed. Such changes, for example a change in the placement and/or routing of a circuit, are common in the iterative design process. Unfortunately, in the prior art, such a change generally required repeating the entire reduction process.
SUMMARY OF THE INVENTION
Therefore, it would be advantageous to provide a computer controlled methodology for combining reduced-order models of interconnected circuits together without the need to recompute the reduced order model of each circuit. A further need exists for a method of storing necessary information for combining circuits with a circuit's reduced order model. A still further need exists for a method of combining reduced order models that produces a reduced order model that is compatible with existing uses of reduced order models.
Embodiments of the present invention provide an advantageous methodology for combining reduced-order models of interconnected circuits together without the need to recompute the reduced order model of each circuit. Additional embodiments provide a method of storing necessary information for combining circuits with a circuit's reduced order model. Further embodiments of the present invention provide a method of combining reduced order models that produces a reduced order model that is compatible with existing uses of reduced order models.
More specifically, a computer implemented method of producing a reduced order model of an electronic circuit to model the connection of two or more circuits is disclosed. Arnoldi reduced order models for nodes of circuits to be interconnected may be computed. A set of modified nodal analysis matrices for the combination of the two circuits may be constructed. A rank one update may be applied to the modified set of nodal analysis matrices to produce a reduced order model of the combined electronic circuits. In this novel manner, a reduced order model for a combination of circuits may be produced from the individual reduced order models of the individual circuits without the need to recompute the reduced order models of the original circuits, and without the need of the original parasitic network models. The resulting reduced order model may be used in a variety, ways consistent with well known uses of such matrices within the field of electronic design automation.
Embodiments of the present invention provide a method of synthesizing an electronic circuit resulting from a combination of circuits based on combining reduced order models of the individual circuit elements.
Another embodiment of the present invention provides a method of placing an electronic circuit resulting from a combination of circuits based on combining reduce order models of the individual circuit elements.
Yet another embodiment of the present invention provides a method of performing a timing analysis of an electronic circuit resulting from a combination of circuits based on combining reduce order models of the individual circuit elements.
REFERENCES:
patent: 5930499 (1999-07-01), Chen et al.
patent: 6041168 (2000-03-01), Hasegawa
Jaimoukha, I.M., et al., “Numerical solution of large scale
Bever Hoffman & Harms LLP
Harms Jeanette S.
Synopsys Inc.
Whitmore Stacy A.
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