Methodology for performing register read/writes to two or...

Details Methodology for performing register read/writes to two or... Methodology for performing register read/writes to two or...

2008-07-15

2008-07-15

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

Reexamination Certificate

active

07401164

ABSTRACT:
Disclosed is a process for controlling the expander cores of a dual expander using a single test port, such as a J-tag port. Access to and control of each expander core is accomplished by placing one of the cores in a bypass mode and accessing and controlling the other core through data supplied serially through the J-tag port.

REFERENCES:
patent: 2005/0120269 (2005-06-01), Larson et al.
CYGNAL Application Note, Programming FLASH through the JTAG Interface, Jul. 2002.
IEEE Std 1149.1-2001 (Revision of IEEE Std 1149.1-1990), IEEE Standard Test Access Port and Boundary-Scan Architecture, Jul. 21, 2001.
IEEE Std. 1149.1-2001 (Revision of IEEE 1149.1-1990), IEEE Standard Test Access Port and Boundary Scan Architecture, Jul. 21, 2001: pp. 1-24 and 36-67.

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