Methodology for image fidelity verification

Details Methodology for image fidelity verification Methodology for image fidelity verification

2007-12-04

2007-12-04

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C716S030000, C716S030000

Reexamination Certificate

active

10908724

ABSTRACT:
A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-dimensional printed image of the critical width integrated circuit segment is simulated. The method then includes determining a ratio of perimeters or areas of the designed critical width integrated circuit segment to the simulated printed critical width integrated circuit segment, and predicting functionality of the critical width integrated circuit segment after printing based on the ratio of perimeters or areas.

REFERENCES:
patent: 5965306 (1999-10-01), Mansfield et al.
patent: 6042257 (2000-03-01), Tsudaka
patent: 6370679 (2002-04-01), Chang et al.
patent: 6373975 (2002-04-01), Bula et al.
patent: 6453457 (2002-09-01), Pierrat et al.
patent: 6757645 (2004-06-01), Chang et al.
patent: 7043712 (2006-05-01), Mukherjee et al.
Graur et al, “Image Fidelity Verification-ContourIVF”, Proceedings of SPIE, vol. 5379, May 3, 2004.
Xiong et al, “Is Gate Line Edge Roughness a First-Order Issue in Affecting the Performance of Deep Sub-Micro Bulk MOSFET Devices?”, IEEE Transactions on Semiconductor Manufacturing, vol. 17, No. 3, Aug. 2004.
Chen et al, “Analysis of the Impact of Proximity Correction Algorithms on Circuit Performance”, IEEE Transactions on Semiconductor Manufacturing, vol. 12, No. 3, Aug. 1999.
Qian et al; “Advanced Physical Models for Mask Data Verification and Impacts On Physical Layout Synthesis”, Proceedings of the Fourth International Symposium on Quality Electronic Design, 2003.
Phil Oldiges, Qinghuang Lin, Karen Petrillo, Martha Sanchez, Meikei Ieong, Mike Hargrove, “Modeling Line Edge Roughness Effects in sub 100 Nanometer Gate Length Devices” IEEE 0-7803-6279, 2000, pp. 131-134.
Title: “New Concepts In OPC” Nick Cobb and Yuri Granik Mentor Graphics Corp., San Jose, California 11 Pages, May 2004.

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