Methodology for generating a modified view of a circuit layout

Details Methodology for generating a modified view of a circuit layout Methodology for generating a modified view of a circuit layout

2006-07-11

2006-07-11

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07076759

ABSTRACT:
A method for generating a modified view of a circuit layout. In a first step, the method includes receiving the circuit layout from a design rule clean database. In a second step, the method includes extracting a base wafer layout from the circuit layout according to a set of computer executable instructions. In a third step, the method includes modifying the base wafer layout according to the set of computer executable instructions.

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“Using ‘empty space’ for IC congestion relief”, By Tsu-Wei Ku, Eedesign, Jun. 19, 2003, pp. 1-7.

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