Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-02
2006-05-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S016000, C331S00100A, C331S052000, C331S057000, C331S1070DP, C327S182000, C327S191000, C327S548000
Reexamination Certificate
active
07039885
ABSTRACT:
Methods are described that involve characterizing an oscillator's jitter or phase noise over a plurality of the oscillator's effective number of delay stages. The oscillator comprises a series of delay stages. Each one of the effective number of delay stages, if selected for the oscillator, describes a respective permissible range of inverter drive strengths that may be used within each delay stage of the oscillator to achieve a respective jitter or phase noise characteristic.
REFERENCES:
patent: 4884041 (1989-11-01), Walker
patent: 5475344 (1995-12-01), Maneatis et al.
patent: 5673008 (1997-09-01), Sumita
patent: 5841325 (1998-11-01), Knotts et al.
patent: 5949292 (1999-09-01), Fahrenbruch et al.
patent: 6005448 (1999-12-01), Pickering et al.
patent: 6008700 (1999-12-01), Pietrzyk
patent: 6304149 (2001-10-01), Kim
patent: 6329849 (2001-12-01), Czarnul et al.
patent: 6462623 (2002-10-01), Horan et al.
patent: 6549081 (2003-04-01), Le et al.
patent: 2002/0136343 (2002-09-01), Cranford, Jr. et al.
patent: 2003/0227333 (2003-12-01), Schmitt et al.
patent: WO01/37429 (2001-05-01), None
Le et al., “Improved ring oscillator design techniques to generate realistic AC waveforms for reliability testing”, 2000 IEEE International Integrated Reliablity Workshop Final Report, Oct. 23, 2000, pp. 155-157.
Seog-Jun Lee Beomsup Kim and Kwyro Lee, “A Novel High-Speed Ring Oscillator For Multiphase Clock Generation Using Negative Skewed Delay Scheme”, IEEE Journal Of Solid-State Circuits, vol. 32, No. 2, Feb. 1997, pp. 289-291.
Chan-Hong Park, and Beomsup Kim, “A Low-Noise, 900-MHZ VCO In 0.6um CMOS”, IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 586-591
Lizhong Sun and Tadeusz A. Kwasniewski, “A 1.25-GHz, 0.35-um Monolithic CMOS PLL Based On A Multiphase Ring Oscillator”, IEEE Journal of Solid-State Circuits, vol. 36, No. 6, Jun. 2001, pp. 910-916.
Toby K.K. Kan, Gerry C.T. Leung, Howard C. Luong, “A 2-V 1.8-GHz Fully Integrated CMOS Dual-Loop Frequency Synthesizer”, IEEE Journal of Solid-State Circuits, vol. 37, No. 8, Aug. 2002, pp. 1012-1020.
Ali Hajimiri and Thomas H. Lee, “A General Theory of Phase Noise in Electrical Oscillators”, IEEE Journal Of Solid-State Circuits, vol. 33, No. 2, pp. 179-194, Feb. 1998.
Ali Hajimiri, Sotirios Limotyrakis and Thomas H. Lee, “Jitter and Phase Noise in Ring Oscillators”, IEEE Journal of Solid-State Circuits, vol. 34, No. 6, pp. 790-804, Jun. 1999.
Barcelona Design, Inc.
Blakely , Sokoloff, Taylor & Zafman LLP
Kik Phallaka
Siek Vuthe
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