Methodology for debugging RTL simulations of processor based...

Details Methodology for debugging RTL simulations of processor based... Methodology for debugging RTL simulations of processor based...

2003-11-12

2008-08-05

Chu, Gabriel (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C717S128000, C703S028000

Reexamination Certificate

active

07409602

ABSTRACT:
An apparatus comprising an analysis block, a graphic user interface and a memory circuit. The analysis block may be configured to generate debug information in response to (i) a command input, (ii) one or more simulation outputs, and (iii) one or more compiler outputs. The graphic user interface may be configured (i) to present the command input in response to one or more user input parameters and (ii) to display the debug information. The memory circuit may be configured to store the one or more simulation outputs and said one or more compiler outputs.

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