Methodology and apparatus for reduction of soft errors in...

Details Methodology and apparatus for reduction of soft errors in... Methodology and apparatus for reduction of soft errors in...

2011-05-17

2011-05-17

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Reliability

Parasitic prevention in integrated circuit structure

C326S014000, C326S026000

Reexamination Certificate

active

07944230

ABSTRACT:
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.

REFERENCES:
patent: 4914629 (1990-04-01), Blake et al.
patent: 4956814 (1990-09-01), Houston
patent: 6058041 (2000-05-01), Golke et al.
patent: 6111780 (2000-08-01), Bertin
patent: 2005/0134323 (2005-06-01), Nash

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