Methodology and apparatus for implementing write combining

Details Methodology and apparatus for implementing write combining Methodology and apparatus for implementing write combining

2008-04-01

2008-04-01

Kindred, Alford (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S030000

Reexamination Certificate

active

07353301

ABSTRACT:
Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

REFERENCES:
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patent: 2003/0023666 (2003-01-01), Conway et al.
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Thomas R. Craver, “Hyper-Threading Technology and Write Combining Store Buffers: Understanding, Detecting, and Correcting Performance Issues”, Intel Software Network, Jul. 18, 2005, http://www.intel.com/cd/ids/developer/asmo-na/eng/20465.htm?pm=Y., 11 pages.
Raoul A.F. Bhoedjang, et al., “User-Level Network Interface Protocols”, IEEE, Nov. 1998, pp. 53-60.

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