Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1996-07-29
1998-01-13
Niebling, John
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438624, 438637, 438722, 438740, 438970, H01L 2128
Patent
active
057079013
ABSTRACT:
An etch stop layer prevents damage to the underlying semiconductor material or metallization layer during etching of a dielectric layer overlying the etch stop layer. The etch stop layer, aluminum nitride or aluminum oxide is used underlying silicon dioxide to prevent damage to the semiconductor material during a fluorocarbon based etch of the silicon dioxide. The etch stop layer is also used underlying a silicon dioxide layer and overlying a titanium nitride or titanium tungsten layer used in metallization to prevent etching of the titanium nitride or titanium tungsten layer during etching of the silicon dioxide.
REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 4824803 (1989-04-01), Us et al.
patent: 4855247 (1989-08-01), Ma et al.
patent: 4861732 (1989-08-01), Fujimura et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 5001076 (1991-03-01), Mikkelson
patent: 5112766 (1992-05-01), Fujii et al.
patent: 5118382 (1992-06-01), Cronin et al.
patent: 5240871 (1993-08-01), Doan et al.
patent: 5270263 (1993-12-01), Kim et al.
patent: 5284549 (1994-02-01), Barnes et al.
patent: 5381046 (1995-01-01), Cederbaum et al.
patent: 5451543 (1995-09-01), Woo et al.
S. Wolf, "Silicon Processing for the VLSI Era, vol. 1", Lattice Press, pp. 182-185, 191-194, 1986.
S. Wolf, "Silicon Processing for the VLSI Era, vol. 2", Lattice Press, 1986, pp. 555-556.
S. Wolf, "Silicon Processing for the VLSI Era, vol. 2", Lattice Press, 1990, pp. 124-125.
S. Subbanna et al., "A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic", IEEE, 1993, pp. 441-444.
R.D.J. Verhaar et al., "A 25 .mu.m2 Bulk Full CMOS SRAM Cell Technology with Fully Overlapping Contacts", IEEE, 1990, pp. 473-476.
Cho Jae-shin
Saha Naresh
Bilodeau Thomas G.
Chen George C.
Jackson Miriam
Motorola Inc.
Niebling John
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