Semiconductor device manufacturing: process – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2002-08-19
2003-08-19
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Radiation or energy treatment modifying properties of...
C438S586000, C438S597000, C438S707000, C438S710000
Reexamination Certificate
active
06607993
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to manufacturing integrated circuits and more particularly to improving gate dielectrics in integrated circuits.
2. Background Art
Integrated circuits are now used in almost every type of product imaginable by the millions. They are used in everyday consumer products such as Game Boy® toys, wired and wireless telephones, home electrical appliances and computers, automobiles, etc. In industrial products, they are used in computer systems, control systems, etc.
Integrated circuits are generally formed in and on a semiconductor substrate of silicon. A gate dielectric is formed under a gate electrode and on the semiconductor substrate over a region within the substrate, which will serve as a channel region of an integrated circuit. The integrated circuits function when the channel region formed in the semiconductor substrate is biased to allow a current to flow from a source region to a drain region by way of the channel region. A gate voltage applied to the gate on top of the gate dielectric film provides the necessary bias. When the applied gate voltage exceeds the threshold voltage of the integrated circuit, current flows laterally from the source region to the drain region through the channel region, and the integrated circuit is turned “on”.
The quality and integrity of the gate dielectric is critical to the functionality of the integrated circuit devices, which include a very tightly defined set of operational characteristics that, in turn, are very sensitive to the characteristics of the materials and process operations used to form the integrated circuit devices. It is important, therefore, to maintain the operational characteristics of a gate dielectric film, and specifically, to suppress any changes associated with the fixed electrical charge of a gate dielectric film and the interface region formed between the gate dielectric film and the underlying substrate surface.
A thermally grown oxide film, commonly used as a gate dielectric material in the semiconductor processing industry, carries with it an electrical charge, called a “fixed oxide charge”. This fixed oxide charge influences the threshold voltage required for turning on a integrated circuit device. If the charge associated with the gate it is too high, due to trapped electrical charges, the characteristics of a film will be destroyed.
Defects, such as impurities and dangling or broken bonds, within the oxide film form “trap sites” or “traps”. Traps within a gate oxide film can exist at the gate electrode/oxide interface, the bulk oxide film, or the oxide/substrate interface. Interface traps located at the oxide/substrate interface are especially prevalent. This is so because, during formation of the oxide film, a transition region forms between the crystalline silicon and the amorphous gate oxide. As a result the transition region includes many incompletely bonded species, which constitute trap sites. These trap sites are usually uncharged, but can become charged when electrons and holes are introduced into the oxide and become trapped at the trap site. One way the traps become charged is by avalanche injection of highly energetic electrons into the oxide. These highly energetic electrons are commonly called “hot carriers”. Hot carriers are generally a result of plasma processes.
The gate dielectric is the heart of an integrated circuit and its integrity is a key reliability requirement for the integrated circuit. The gate dielectric must have high integrity, which means it must not have any pinholes or surface irregularities. Pinholes and surface irregularities will cause uncontrolled current flow in the semiconductor substrate and to the gate resulting in failure of the integrated circuit.
Gate dielectric integrity has become increasingly more important as the industry has pushed for greater miniaturization of the integrated circuits to produce smaller and more powerful products. This has required the gate dielectric to be thinner and thinner, which means that the pinholes and surface irregularities cause more and more problems.
In the past, gate dielectric improvement was achieved by methods, which were primarily preventative in nature; i.e., cleaner processes, less damaging processes, more conservative (and less competitive) designs, etc.
Solutions to these problems with the gate dielectric have long been sought, but have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method for manufacturing an integrated circuit including a substrate with a gate layer and a gate dielectric provided on the substrate. The gate layer is formed into a gate using a process that imposes a charge in the gate dielectric. The substrate, gate, and gate dielectric are irradiated to discharge the charge across the gate dielectric. This method of manufacturing produces a thin gate dielectric with high integrity and without pinholes and/or surface irregularities, which would cause the gate dielectric to fail.
REFERENCES:
patent: 5447875 (1995-09-01), Moslehi
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5956597 (1999-09-01), Furukawa et al.
patent: 6281593 (2001-08-01), Brown et al.
patent: 6440756 (2002-08-01), Shohet et al.
Dickinson Ronald
Qi Dong Xiang
Rajgopal Rajan
Teo Yeow Meng
Chartered Semiconductor Manufacturing Ltd.
Ishimaru Mikio
Nguyen Ha Tran
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