Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-12-02
2001-04-03
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S238500, C714S718000, C714S719000
Reexamination Certificate
active
06212112
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for verifying the integrity of decoding circuits of a memory, and, more particularly, to a diagonal test performed during production testing of the memory.
BACKGROUND OF THE INVENTION
An important step during the manufacture of an integrated circuit is to verify operation of the circuit at the end of production. Given the number and size of transistors formed in an integrated circuit, it is not rare for an impurity to be deposited either on a manufacturing mask or on the silicon wafer during manufacture, thus causing an error in the circuit. These errors are expressed in different ways, such as a connection fault, a short-circuit or a defective transistor. In general, signals are said to be either stuck between two signals or, more generally, stuck at a logic level 1 or 0.
The integration density in a memory is typically at a maximum and the risk of a signal being stuck is thereby increased. Many tests have been prepared for carrying out individual tests on all the functional elements of the memory. Since the testing time has to be reduced for cost reasons, the fastest tests are carried out for enabling detection of a maximum number of errors so that the total tests are performed only on the valid components.
One of the first tests performed on a memory includes verifying the integrity of the storage matrix. Testing the integrity of the storage matrix is one of the shortest tests and, therefor, enables the defective components to be sorted out faster. However, the other elements of the memory must also be tested. This makes it possible to carry out the other tests while assuming the storage matrix works properly.
To ascertain the integrity of the decoding circuits, there are known methods in the prior art for carrying out the test of the diagonal, hereinafter referred to as the diagonal test. The diagonal test includes placing all the storage cells in a first state. Then, all the storage cells located on the diagonal of the storage matrix are placed in a second state.
FIG. 1
shows a square type matrix
1
having storage cells
2
. The contents of the storage cells
2
are indicated on each cell. All these cells contain a logical level 0 except for the cells of the diagonal of the matrix
1
, which contains a logic level 1.
The diagonal test ends with a reading of each storage cell to ascertain that there is no multiple decoding of rows or columns. A multiple decoding results in an erroneous reading of the contents of certain cells. When an error occurs during the writing, two bits or no bits are written simultaneously instead of a single bit for converting a 0 into 1, or vice versa. Similarly, when a decoding error occurs during the reading, several cells are read simultaneously and the information read is the result of an AND or OR logic function between the data that is simultaneously read. The logic function is dependent on the type of memory and/or on the error.
The diagonal test is very efficient for a square storage matrix, i.e., a matrix having as many rows (word lines) as columns (bit lines). However, it is common to have rectangular storage matrices, wherein the number of rows and columns are different. Referring to page access memories, the corresponding memory has 512 columns regardless of its total capacity. Conventionally, a page has 64 eight-bit words. The diagonal test then takes the form shown in
FIGS. 2 and 3
. The rectangular matrix is divided into several square matrices.
As readily understood by one skilled in the art when referring to
FIGS. 2 and 3
, the patterns written are repeated for different addresses. This is all the more troublesome as the pattern is repeated for addresses where only one bit changes. It is therefore not possible to carry out a valid test for decoding this single bit because the changing of this bit amounts to the testing of an identical memory zone.
In certain cases, the memory may even be subdivided into a larger number of squares. At present, there are page accessible memories having a size ranging between 1 kb and 16 Mb, which results in a variable number of lines for a fixed number of columns. In certain cases, the number of squares repeated is greater and results in the non-testability of the decoding of a large number of addressing bits. Furthermore, the memories most subject to non-rectangular sizes are generally organized in words, while others are even configurable according to several word sizes.
SUMMARY OF THE INVENTION
The invention improves testing of a memory by taking advantage of the word organization of the memory. The method makes it possible, first, to overcome the uncertainties of the testing as described above, and, second, to reduce the testing time.
An object of the present invention is thus to provide a method for verifying the integrity of the decoding circuits of a memory comprising a storage matrix including N rows and M columns of L-bit words. The storage matrix has N*M*L storage cells accessible by N*M addresses per L-bit word. The variables N, M and L are positive integers greater than 1. After all the words of the memory have been written with the same first word, at least N or M operations for writing second words are performed in the storage matrix in such a way that each row and each column has at least one second recorded word. The second words are different from the first words. All the words of the storage matrix are read.
The method of the present invention reduces the number of write operations and the number of address bits whose decoding is not verifiable by the size of the words when a test is made on the memory having a small number of rows. If several second words are written on the same row or in the same column, then it is useful that the second words are different. This makes it possible to reduce the risk of non-testability of the decoding of an address bit to zero.
One improvement for a memory that has a page write mode includes the fact that a plurality of different second words are written simultaneously on the same row. The second words are written on the diagonals of storage blocks, with each block having as many rows of words as it has columns of words. The use of a block write algorithm makes it possible to overcome the shape of the storage matrix.
Another object of the present invention is to provide a memory device comprising a storage matrix including N rows and M columns of L-bit words, and decoding circuits for selecting cells of the memory. The memory further comprises a test circuit for implementing the method of the invention and verifying the integrity of the decoding circuits of the memory.
REFERENCES:
patent: 5481499 (1996-01-01), Meyer
patent: 5490115 (1996-02-01), Shah et al.
patent: 5954831 (1999-09-01), Chang et al.
patent: 5996106 (1999-11-01), Seyyedy
“High Coverage Three-Pattern Dram Test” IBM Technical Disclosure Bulletin, vol. 36, No. 2, Feb. 1, 1993, pp. 225-228, ISSN: 0018-8689.
Van De Goor et al.: “Locating Bridging Faults in Memory Arrays” Proceedings of the International Test Conference, Nashville, Oct. 28-30, 1991, Jan. 1, 1991,pp. 685-694, IEEE ISBN: 0-8186-9156-5.
Bappert et al.: “Memory Testing”, IBM Technical Disclosure Bulletin, vol. 19, No. 5, Oct. 1976, p. 1621 XP002116220, IBM Corp. New York.
Moncada Frederic
Naura David
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore G.
Mai Son
STMicroelectronics S.A.
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