Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-10-23
2001-11-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06317852
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention applies to testing of semiconductor memories and in particular testing auto-refresh and self refresh circuitry for Synchronous DRAM's.
2. Description of Related Art
During an auto-refresh for a SDRAM (Synchronous DRAM) an address from the internal counter is decoded to turn on a word line. All cells along the word line are refreshed After the refreshing is complete the word line is automatically turned off and the internal counter is incremented by one. The same process happens in a self refresh operation, except the self refresh operation is executed every sixteen microseconds. It is very difficult to test auto-refresh or self refresh for a SDRAM because the refresh operations are self timed. During refresh the word line address is also difficult to read to know which word line is being refreshed.
Involved in refreshing a SDRAM are the internal counter, auto-refresh control logic and self refresh control logic. If the counter is incremented by one after either an auto-refresh or a self refresh, then it has been held that the refresh circuitry worked properly.
In U.S. Pat. No. 4,672,583 (Nakaizumi) a DRAM (dynamic random access memory) is equipped with a test circuit for testing the internal refresh circuitry. An internal address counter is used to supply an address to both the row and column address decoders such that one memory cell is designated along a diagonal in the memory cell array. Each designated memory cell is written into and then read to insure the correct data was written. Referring to U.S. Pat. No. 5,321,661 (Iwakiri et al.), test circuitry is included on a DRAM to allow testing of the on chip refresh circuitry. In U.S. Pat. No. 5,625,597 (Hirose) test circuitry is included on a DRAM to test the refresh counter and to the counter cycle at time of refresh.
It is the purpose of this invention to present a method to test auto-refresh circuitry and a similar method to test self refresh circuitry in an easy and concise way for an SDRAM. It is further a purpose of this invention to be able to accurately determine on which word line a refresh failure occurred.
SUMMARY OF THE INVENTION
“In the present invention a method is described for testing” the auto-refresh and the self refresh of an SDRAM. The two methods are a slight variation on one another caused by the differences between the two operations in which the self refresh is self timed to occur every few microseconds. In the method for self refresh, it is not necessary to wait until the self refresh cycle is complete. Exit of the self refresh command can be done after a memory row has been refreshed in the test mode. No additional circuitry is needed to perform either the auto-refresh or the self refresh test, and the row and column address do not need to be in any particular relationship with one another.
In the method for testing the auto-refresh mode, the SDRAM is initialized with a logical “1” written into every memory cell. Then an MRS (mode register set) command is issued and the chip is set into a test mode. A row active command is issued to activate a word line by using the address from an internal counter. A logical “0” is written to a column of the memory array using write with auto-precharge command where the logical “0” is written into a cell corresponding to the column along a word line addressed by the internal counter. The write with auto-precharge command writes column data to the cells along a word line and then turns off the word line. Only the single cell corresponding to the column address is written with a logical “0”. All other cells along the word line contain a logical “1” written during initialization of the chip.
When testing the auto-refresh mode, an auto-refresh command is issued which increments the internal counter used to address the word lines. If the last word line has not been tested, a column containing a logical “0” is written into a corresponding cell along a word line being addressed by the internal counter. The internal counter is incremented until the last word line is tested. If the last word line has been tested, an MRS command is issued and the test mode is turned off. Similarly, when testing self refresh, a self refresh command is issued to increment the internal counter to address the word lines. If the last word line has not been tested, a column address is used to write a logical “0” into a cell. The internal counter is incremented by self refresh, and the self refresh mode is exited. This is repeated until a logical “0” has been written into a cell in every word line. By exiting self refresh after the internal counter is incremented saves test time by not waiting for a whole self refresh cycle to complete.
Next each word line is turned on in sequence and the cells along each word line are read using read with auto-precharge which reads the word and then turns off the word line. A test signature is formed by the logical zeros written into one cell along each word line. Comparing this signature with the signature that should exist provides an easy way to determine if there is a test error and where the error occurred.
Testing auto-refresh is the same process as testing self refresh except the internal counter is incremented using the auto-refresh command, and there is no step to exit auto-refresh after incrementing the internal counter. Similar to self refresh, a test signature is formed by the logical zeros written into one cell along each word line. Comparing this signature with the signature that should exist provides an easy way to determine if there is a test error and where the error occurred.
REFERENCES:
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patent: 5450364 (1995-09-01), Stephens, Jr. et al.
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Lau Hon-Shing
Oh Yaw T.
Ackerman Stephen B.
De'cady Albert
Saile George O.
Torres Joseph
Vanguard International Semiconductor Corporation
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