Method to suppress subthreshold leakage due to sharp isolation c

Details Method to suppress subthreshold leakage due to sharp isolation c Method to suppress subthreshold leakage due to sharp isolation c

1995-10-11

2000-11-07

Ngo, Nagan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

061440817

ABSTRACT:
A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

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Nesbit, L.A., "Method of Forming Shallow Trench Isolation with Selectively Doped Sidewalls", IBM Tech. Disc. Bulletin vol. 31, No. 2, Jul. 1988, pp. 418-420.
Wen, D. S., "Optimized Shallow Trench Isolation Structure and Its Process for Eliminating Shallow Trench Isolation-Induced Parasitic Effects", IBM Tech. Disc. Bulletin vol. 34, No. 11, Apr. 1992, pp. 276-277.

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