Method to statically balance SOI parasitic effects, and...

Details Method to statically balance SOI parasitic effects, and... Method to statically balance SOI parasitic effects, and...

2000-06-22

2001-07-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06262911

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to Static Random Access Memories (SRAMs), and more specifically relates to a method to statically balance Silicon-On-Insulator (SOI) parasitic effects, and eight device SRAM cells that use the method.
2. Background Art
Many transistors were previously created by forming each transistor in a “well” of silicon or directly in “bulk” silicon. The wells were specifically doped to both create each transistor and to isolate each transistor from other devices. Although the wells did have some isolation capabilities, these capabilities were and are less than ideal.
Recently, there has been a move to create Silicon-On-Insulator (SOI) integrated circuits. In a SOI integrated circuit, a transistor is formed over an insulator. The insulator completely isolates the transistor from other devices on the integrated circuit and from the “bulk” silicon or substrate. Because of the excellent isolation of SOI technologies, there are quite a bit of performance improvements that are realized when SOI is used instead of well or bulk technologies. The speed improvements for a logic circuit can be as high as
30
percent over the same circuit designed with previous technologies.
Even with these speed improvements, there are some detriments to SOI technologies. For a transistor designed with SOI methods, the body of the transistor will be “floating” because of its extreme isolation from other components. In analog circuitry, such as amplifiers, sense amplifiers, etcetera, where a good balance between transistors is required, the effects of a floating body can create differences that can cause faults. Some of these faults are caused by “parasitic” effects. These effects are called “parasitic” effects because they are unwanted and are detrimental to the circuit. For instance, in Static Random Access Memories (SRAMs), there are differential circuits that are connected to long arrays of cells. These differential circuits depend on balance between their inputs; any imbalance can cause erroneous data or slow the circuit. The parasitic effects of SOI transistors create imbalances in the differential circuits.
What is needed is a method to balance the parasitic effects of SOI transistors in balanced circuits such as SRAM circuits, and also needed are SRAM circuits using the method.
DISCLOSURE OF THE INVENTION
The preferred embodiments of the present invention provide a method to statically balance Silicon-On-Insulator (SOI) parasitic effects, and provide eight device Static Random Access Memory (SRAM) cells using the method. The present invention overcomes limitations of the prior art by providing a balanced output stage that creates a particular set of parasitic effects, as seen by a node connected to the output of the balanced output stage. If the balanced output stages are used at both outputs of a SRAM cell, the nodes to which the outputs of the balanced output stages are connected will see the same parasitic effects when the transistors in the balanced output stages are off. Thus, the balanced output stages can create the same effect on both the true and complement bitlines of an SOI SRAM, thereby balancing both of these lines and improving access times and functionality.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.


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IBM Technical Disclosure Bulletin, “Eight Device Storage Cell”, Feb. 1973, pp. 2861-2862.

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