Method to shrink cell size in a split gate flash

Details Method to shrink cell size in a split gate flash Method to shrink cell size in a split gate flash

2006-04-18

2006-04-18

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S719000, C438S723000, C438S724000, C438S753000, C438S756000, C438S757000, C438S770000, C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

07030020

ABSTRACT:
A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the dielectric layer. A patterned masking layer with an opening is formed overlying the polysilicon layer. Through the opening, the polysilicon layer is oxidized to form a first silicon oxide layer at the bottom of the opening. Thereafter the masking layer is removed and the polysilicon layer is exposed. The exposed polysilicon layer is then etched through using the first silicon oxide layer as a mask to form MOS floating gates. The first silicon oxide layer is then removed. A second conductor layer is then deposited overlying the MOS floating gates for forming control gates.

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