Method to share memory in a single chip multiprocessor system

Details Method to share memory in a single chip multiprocessor system Method to share memory in a single chip multiprocessor system

1998-10-21

2001-02-27

An, Meng-Ai T. (Department: 2783)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S170000, C711S153000

Reexamination Certificate

active

06195733

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of data processing systems and particularly to a shared memory structure for a multiprocessor system.
2. Prior Art
Communications processing in modems, digital cellular phones and the like typically employs a microprocessor controller and one or more digital signal processing (DSP) co-processors. It is desirable to provide a processing system that integrates all communications processing functions on a single integrated circuit. Due to limitations on the number of pins in a package and the long access times to access data from external memory, it is a practical necessity for one or more processors in a single chip multi-processor to execute from internal memory, as well as use internal memory to maintain data. It is necessary to load program code from external memory into the internal memories and execute from them, and at the same time permit relocation of code within the pages of internal memory to facilitate runtime process switching.
Due to the fundamental nature of DSP computations, the integration of data and program memories with the DSP engines on a single chip can provide significant savings in cost and power dissipation. On the other hand, on-chip random access memory (RAM) is very “expensive” in terms of power requirements and silicon area. One alternative is to use programmed read only memory (ROM) for the DSP engines; however, this makes product maintenance and development more difficult. The present invention provides a unique memory architecture that addresses these conflicting requirements.
SUMMARY OF THE INVENTION
The present invention is directed to a data processing system having at least two independent processors. Each of the processors has a private data bus and a private program bus. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space. This permits the program code to be loaded into any available page, and the processors can execute the code regardless of where it has been loaded, thereby permitting easy relocatability.


REFERENCES:
patent: 5539896 (1996-07-01), Lisle
patent: 5579503 (1996-11-01), Osborne
patent: 5611075 (1997-03-01), Garde
patent: 5909702 (1999-06-01), Jalfon et al.

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