Method to selectively form poly SiGe P type electrode and...

Details Method to selectively form poly SiGe P type electrode and... Method to selectively form poly SiGe P type electrode and...

2005-03-29

2005-03-29

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S153000, C438S199000

Reexamination Certificate

active

06872608

ABSTRACT:
A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.

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CS-01-093 U.S. Appl. No. 10/266,425, filed Oct. 8, 2002 to Chew-Hoe Ang et al., “Dual Si-Ge Polysilicon Gate with Different Ge Concentrations for CMOS Device Optimization”.

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