Method to reduce wire-or glitch in high performance bus...

Details Method to reduce wire-or glitch in high performance bus... Method to reduce wire-or glitch in high performance bus...

1996-04-30

2001-10-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S114000

Reexamination Certificate

active

06310489

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to high performance bus architectures. More specifically, the invention relates to reducing the wire-or glitch in bus design supporting wire-or functions.
(2) Related Art
The “wire-or glitch” is a common problem in bi-directional electrical bus design. For example, where open drain drivers are connected to a bus terminated in pull-up resistor, if one driver turns off at the same time as another driver turns on, a wire-or glitch occurs. The problem is exacerbated by line length and line loading. The wire-or glitch in the above example is a positive going disturbance which occurs when one driver output turns off (goes high) while the other driver turns on (goes low). The glitch is caused by a sudden increase in line current which in turn generates a positive going voltage on the line. Some time is required for the on-going driver's output to drive the current back to the original level. Amplitude and length of the glitch depend on three factors: 1) current that the off-going output was conducting; 2) line impedance; and 3) line length between outputs. The settling time of the glitch is approximately the round trip delay of the loaded bus.
The performance of a bus is often determined in the context of cycle time. The cycle time is described by the equation: cycle time=clock to out+propagation delay of bus+setup of input+clock skew. For a bus performing wire-or functions, the cycle time equation becomes: cycle time=clock to out+two times the propagation delay of bus+set up of input+clock skew.
FIG. 1
a
shows a graph of negative-going wave
11
at the location of the on-going driver of a prior art system.
FIG. 1
b
shows a graph of a positive-going wave
12
at the location of the off-going driver of a prior art system.
FIG. 1
c
shows a graph of a composite wave
13
of a prior art wire-or system. Composite wave
13
corresponds to sampling the bus
3
at the location of the off-going driver at any instant in time. All three signals are shown relative to the powers supply voltage
52
, a high threshold voltage (V
ih
)
51
, a low threshold voltage (V
il
)
50
, and a voltage operation level (V
ol
)
53
. Generally speaking, when the composite wave is below V
il
50
, the bus will be sampled low. When the composite wave is above V
ih
51
, the bus will be sampled high. When the bus falls between V
il
50
and V
ih
51
, an indeterminate condition exists on the bus and it is not possible to sample the bus either high or low. One of ordinary skill in the art will recognize that these two threshold voltages
50
and
51
create a hysteresis in the bus signal. It is desirable to have this range between V
ih
and V
il
quite small because as the range increases, the noise margin on the bus diminishes.
In the prior art, off-going drivers rise uncontrolled to V
TT
. Only the arrival of a negatively reflected wave, two propagation delays later, drags the bus down to where it can be accurately sampled.
FIG. 1
shows a prior art wire-or system in which the rise time and the fall time are not controlled. Wave
11
is a negative going voltage created at the on-going driver (going low). Wave
12
is the positive going wave created by the off-going driver (going high) as it rapidly rises to V
TT
52
before the negative going wave
11
arrives. Wave
13
is the composite wave that can be sampled on the bus at the off-going driver. As can be seen, the arrival of the negative going wave
11
only drives the composite wave down to about V
ih
51
after the propagation delay. Thus, the bus can not be properly sampled until a negatively reflected wave arrives two propagation delays after the initial switching.
In a heavily loaded, long bus, the propagation delay becomes the most significant part of the overall cycle time. For example, the SPARC Center 2,000 work station available from Sun Microsystems of Mountain View, Calif. has ten slot backplane bus which supports wire-or functions at 40 MHz. The loaded bus one-way propagation delay is approximately 5 ns. Therefore, the bus settling time is the round trip of the loaded bus delay, approximately 10 ns. Accordingly, 10 ns of the 25 ns of cycle time are absorbed by the wire-or glitch settling time.
With 16 slots on a 16 inch backplane, the approximate propagation delay rises to 6.5 ns, with a round trip delay of 13 ns. As a demand for higher speed buses increases, the wire-or glitch becomes a critical limitation. It is, therefore, desirable to be able to reduce the wire-or glitch such that only a single propagation delay is required for the wire-or glitch to settle such that the bus can be properly sampled.
BRIEF SUMMARY OF THE INVENTION
A system and method of reducing wire-or glitch to improve bus speeds is disclosed. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver (going high) is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver (going low) is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.


REFERENCES:
patent: 3694665 (1972-09-01), Belluche
patent: 4849659 (1989-07-01), West
patent: 5136187 (1992-08-01), Ceccherelli et al.
patent: 5179299 (1993-01-01), Tipon
patent: 5239559 (1993-08-01), Brach et al.
patent: 5548226 (1996-08-01), Takekuma et al.

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