Method to reduce the power consumption of large PLAs by...

Details Method to reduce the power consumption of large PLAs by... Method to reduce the power consumption of large PLAs by...

2006-06-20

2006-06-20

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S037000, C326S038000, C326S039000, C326S041000

Reexamination Certificate

active

07065732

ABSTRACT:
A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is presented. The method also provides for gating logic to be applied to the first sub-PLA and the second sub-PLA. Power consumption is then controlled in the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption. In another embodiment, a PLA be recursively divided into a plurality of sub-PLAs.

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Khatri et al., “Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric”, Nov. 2002, Computer Aided Design, 2000, ICCAD-2000, IEEE/ACM International Conference on, pp.: 412-418.

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