Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-03-02
2002-02-19
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S058000, C710S059000, C710S033000
Reexamination Certificate
active
06349354
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to bandwidth reclamation on a Universal Serial Bus. More specifically, the invention relates to reducing the system bus throughput load due to universal serial bus bandwidth reclamation.
(2) Related Art
The Universal Serial Bus (USB) is a half duplex single logical wire which permits relatively high speed serial communication between a host system bus and devices on the USB. The USB permits four types of transfers: isochronous transfers, interrupt transfers, control transfers, and bulk transfers.
Isochronous transactions are characterized by a constant fixed data rate between the USB device and the host It is used for devices that continuously consume or produce data at a fixed rate such as microphones or speakers. To support this, the USB guarantees that a required maximum data rate can be transferred in each frame. USB does not require that these transactions occur at this maximum rate in every frame. Failed transactions are not retried. Therefore, the data delivery is not guaranteed in isochronous transactions. Moreover, isochronous data structure elements are always retired after execution.
Interrupt transactions are characterized by small spontaneous transfers from a device. Interrupt transactions are used for devices that require predictable service intervals, but do not produce predictable data flow. Like isochronous transactions, interrupt transactions have a guaranteed maximum data rate. Interrupt transactions are retired after limited retries due to data corruption or other errors.
Control transactions are used to provide a control channel from the host to the USB devices through which control, status, and configuration information may flow. Control transfers always consist of a set-up stage and zero or more data stages followed by a status stage. A stage consists of one or more transactions.
Bulk transactions are characterized by guaranteed transmission of data between client and host under relaxed latency requirements. Bulk transactions are typically used for devices such as printers which can tolerate large latencies, but require movement of large amounts of data. Interrupt, control, and bulk all have guaranteed delivery. Thus, following the data transfer if an acknowledge is not received, the transaction will be retried at the next opportunity.
The USB transfers data in frames. Every frame is one millisecond long and begins with a start of frame packet. The host controller driver can schedule pending transactions with isochronous transactions scheduled first, interrupt transactions next and control and bulk transactions following in turn. USB requires that no more than ninety percent of the frame time be allocated to isochronous and interrupt transactions. Ten percent of each frame must be reserved for control transactions. If, for example, isochronous and interrupt transactions fill up ninety percent of the allocated frame and control transactions fill the remaining ten percent, then no bulk transactions will take place in that frame. Conversely, if during a frame no isochronous transactions are scheduled and no control transactions are pending, bulk transactions are allowed to fill the entire frame. Significantly, if the isochronous and interrupt do not fill their scheduled time, this time may be used for bulk or control transfers. This may occur because scheduling always presumes a worst case transmission characteristic or because there are insufficient transactions of those types to fill the possible 90% allocated. Scheduled transactions which do not follow the worst case profile will result in additional bandwidth available for bulk transactions.
The operations of the USB are generally well known in the art. Architectural details and signaling characteristics are explicitly defined in Universal Serial Bus Specification, Version 1.0, Jan. 19, 1996. Similarly, one possible universal host controller interface (UHCI) is defined for the interface between the USB and a host system bus. Details in that interface are set forth in Universal Host Controller Interface Design Guide, Revision 1.1, March 1996.
Transactions allow data transfer over the USB. Some number of transactions are moved over the bus in each frame. A frame schedule is used by the host controller to determine what specific transactions are moved in what frame. Different implementations of host controllers will require different organization and control of frame schedules.
FIG. 1
shows the diagram of an example prior art frame schedule. A hardware register
101
provides a base address, and a frame counter
102
provides an offset to create an address
103
of a frame pointer
104
in a frame list
105
. Each entry of the frame list
105
includes two additional relevant bits and two unused bits in addition to a frame pointer. A T-bit
107
is used to indicate whether transactions are pending for the frame. A Q-bit
106
indicates whether a frame pointer points to transaction descriptor (TD) or a queue head (QH).
TDs are data structures containing characteristics of the transaction requested on the USB. Even though four types of transfers exist on the USB, all TDs use the same format. Different transfer types are distinguishable by a number of control bits. QHs are data structures to support control, bulk, and interrupt transactions. Because data is guaranteed to have reliable delivery, such transactions must be queued to facilitate retries in the event a transaction is unsuccessful or, in the case of control and bulk, must be deferred to a subsequent frame. The QH sits at the top of a chain of TDs corresponding to pending transactions of a particular transfer type. The format of a standard prior art QH is shown as element
116
. A QH and any associated TDs is a queue context. A QH with no TDs is an empty queue context and is indicated by setting a T-bit of the QH. QHs contain two pointers, a QH link pointer pointing to the next adjacent QH in the schedule and a queue element link pointer pointing to the first TD in the queue.
In executing the frame schedule, the host controller traverses horizontally through the isochronous TDs conducting corresponding transactions. In
FIG. 1
, frame pointer
104
points to isochronous TD
108
, which in turn is linked to the isochronous TD
109
, which is linked to isochronous TD
110
. To be a valid schedule, all isochronous transactions and any interrupt transactions must be traversed during less than 90% of the frame time (all isochronous and interrupt transactions scheduled must be completed in the frame). Thus, the host controller driver creates the schedule assuming a worst case transmission rate and does not schedule more than the allowable amount of transactions of these types. To achieve this, isochronous TD
110
contains a link pointer pointing to QH
111
corresponding to pending interrupt transactions. Interrupt QH
111
contains an element link pointer pointing to TD
115
. The transfer corresponding to TD
115
is completed before the host controller is allowed to follow the QH link pointer of interrupt QH
111
to control QH
112
which in turn points to bulk QH
113
. Bulk QH
113
contains a QH link pointer which points to bulk QH
114
. Depending on the system and scheduling priority, control transactions can be executed by following QH links or queue element limits such that, e.g. one control transaction is attempted before the next QH in the schedule is traversed or all pending control transactions under a QH are attempted (as time permits) before moving to the next QH. The first example is much more common.
If time is available in the frame after isochronous transactions corresponding to TDs
108
-
110
and the relevant transactions corresponding to interrupt and non-reclaimable control QHs
111
,
112
occur, the remaining time will be used for reclaimable control/bulk transactions, corresponding to the TDs under QHs
113
and
114
. This would typically take the form of retrieving QH
113
from main memory identifying TD
123
, retrieving TD
123
and, subsequent
Beausoleil Robert
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Phan Raymond N
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