Method to reduce STI HDP-CVD USG deposition induced defects

Details Method to reduce STI HDP-CVD USG deposition induced defects Method to reduce STI HDP-CVD USG deposition induced defects

2001-09-24

2002-07-30

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S437000

Reexamination Certificate

active

06426272

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing defects in HDP-CVD deposition in the formation of shallow trench isolation in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, shallow trench isolation (STI) is often used to isolate active areas from one another. High density plasma chemical vapor deposition (HDP-CVD) of undoped silicate glass (USG) has been used for STI gap fill for 0.25 &mgr;m generation and beyond. The HDP-CVD process includes a deposition component and a sputtering component. In an HDP plasma process, the dielectric material is deposited and etched simultaneously in the same reaction. This process causes the material to be deposited very densely and with no voids. In addition, the etching process causes the HDP material to assume a near 45 degree angle profile at trench corners. In addition, a densification step is performed.
U.S. Pat. No. 6,165,854 to Wu discloses a thermal oxide liner formed to recover silicon damage during etching. U.S. Pat. No. 6,146,971 to Chen et al teaches a thermal oxide liner having a thickness of 100 to 150 Angstroms. U.S. Pat. No. 6,153,479 to Liao et al also shows a thermal oxide liner. U.S. Pat. No. 6,146,974 to Liu et al forms a thermal oxide liner, followed by an un-biased unclamped HDP oxide liner layer, and then an HDP oxide gap filling layer.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for forming shallow trench isolation regions in the fabrication of integrated circuits.
It is a further object of the invention to provide a shallow trench isolation process where HDP-CVD induced defects are reduced.
Yet another object is to provide a method for shallow trench isolation formation having a thick un-biased HDP USG liner layer to reduce HDP-CVD induced defects.
In accordance with the objects of the invention, a method for shallow trench isolation formation having a thick un-biased HDP USG liner layer to reduce HDP-CVD induced defects is achieved. Trenches are etched through an etch stop layer into a semiconductor substrate. The semiconductor substrate is thermally oxidized to form a thermal oxide liner layer within the isolation trenches. The isolation trenches are filled using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein the HDP-CVD process comprises: first depositing a first liner layer overlying the thermal oxide liner layer wherein no bias power is supplied during the first depositing step and wherein the first liner layer has a thickness of between 250 and 350 Angstroms, second depositing a second liner layer overlying the first liner layer wherein a low bias is supplied during the second depositing step, and third depositing a gap filling layer overlying the second liner layer to fill the isolation trenches. The gap filling layer is polished back overlying the etch stop layer. The etch stop layer is removed to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.


REFERENCES:
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patent: 6146971 (2000-11-01), Chen et al.
patent: 6146974 (2000-11-01), Liu et al.
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